1. Field of the Invention
This invention relates to an electrically erasable and programmable read-only memory (EEPROM) device, and more particularly to a row decoder circuit in the EEPROM.
2. Description of the Related Art
One typical memory cell used in the EEPROM is a tunnel oxide EPROM cell known as an ETOX-type cell (ETOX is an trademark of Intel Corp.).
In EEPROMs employing ETOX-type cells, writing is carried out with a bit unit, and erasing is performed on all bits by applying a high voltage to the sources of all cells at the same time (flash erase), or erasing is is done in the block by simultaneously applying a high voltage to the sources of the cells of the selected block.
FIG. 7 is a sectional view of an ETOX-type cell. Numeral 71 indicates a semiconductor substrate of one conductivity type such as P-type; 72 and 73 source and drain regions of the opposite conductivity type such as N-type, which are selectively provided in the semiconductor substrate 71; 74 a gate insulating film (a tunnel insulating film) provided on the substrate surface; 75 a floating gate (a floating gate electrode) provided above the semiconductor substrate via the gate insulating film 74 between the source and drain regions; and 76 a control gate (a control gate electrode) provided above the floating gate via an interlayer insulating film 77.
The operating principle of the ETOX-type cell has been reported in, for example, S. Mukherjee, et al, "A single transistor EEPROM cell and its implementation in a 512K CMOS EEPROM," IEDM 85, pp. 616-619.
In such a memory cell, during writing (programming) a low voltage (for example, 0V) is given as the source voltage V.sub.S ; a low voltage (for example, 0V) is applied to the substrate 71; a high voltage V.sub.pp (for example, 12V) is given as the control gate voltage V.sub.CG ; and a high voltage is applied as the drain voltage V.sub.D. Then, an on-current flows between the drain and source regions, producing pairs of hot electrons and hot holes in the vicinity of the drain region. Those holes flow into the substrate 71 as a substrate current. However, hot electrons are injected into the floating gate 75 to increase the threshold level with respect to the control gate 76, thereby completing the writing operation.
Erasing of data is carried out by applying the high voltage V.sub.pp and a low voltage (for example, 0V) to the source region 72 and the control gate 76, respectively, and setting the drain region to, for example, a floating condition. At this state, a floating gate potential V.sub.FG is set according to both the ratio of the capacity between the control gate 76 and the floating gate 75 to the capacity between the floating gate 75 and the source region 72, and the source voltage V.sub.S. Therefore, Fowler-Nordheim tunnel current flows through the thin tunnel insulating film 74 (approximately 10 nm) provided between the source region 72 and floating gate 75. Thus, electrons are reduced from the floating gate 75 to complete the erasing operation (the threshold level becomes the condition before writing).
However, the following problems (a) and (b) may occur by applying the high voltage V.sub.pp to the source region 72 during erasing:
(a) Since the high voltage V.sub.pp is applied to the source region 72 during erasing, a junction breakdown voltage at the side of the source region 72 must be increased. For that purpose, it is necessary that the depth of the source region is made deeper than that of the drain region, or that the impurity concentration of the source region is reduced. The deeper source region would have an adverse effect on device scaling. In fact, when cells designed according to the same design standards are compared in terms of gate length, the gate length of the ETOX-type cell is nearly 0.2 .mu.m longer than that of the normal EPROM cell. PA1 (b) Since the high voltage V.sub.pp is applied to the source region 72 during erasing, hot holes are generated near the source region. Some of those hot holes are trapped into the tunnel insulating film 74, reducing the reliability of the cell. PA1 (a) The stress applied to the gate oxide film of the P-channel transistor 83 is large. PA1 (b) Since the conductance gm of the P-channel transistor 83 is low, the operation speed of the word line driver is reduced. PA1 (c) Since it is necessary to apply the negative voltage to the gate of the P-channel transistor 83 continuously, it is required to operate the negative charge pump circuit 85 usually. Therefore, the stand-by current can not be reduced to zero. PA1 (a) During the writing operation, a high voltage of, for example, 12V is applied to the selected word line, and the unselected word line must be kept at a grounded condition. Therefore, it is necessary that the substrate potential of the P-channel transistor 83 is 12V or more. In this state, for applying the ground potential to the unselected word line through the P-channel transistor 83, it is necessary to apply a high negative voltage (for example, -4V) to the gate of the P-channel transistor 83. At this time, a very high voltage, given by 16V is applied to the gate oxide film of the P-channel transistor 83. For the gate oxide film of the P-channel transistor 83, therefore, there is needed a film thickness (for example, 50 nm) so as not to be subjected to breakdown. Considering that the thickness of the gate oxide film used in transistors designed by 0.8 .mu.m rule is of the order of 20 nm, the application of the thicker thickness to the gate oxide film of the P-channel transistor 83 goes against the device scaling. In addition, if transistors of the memory device are produced in such a manner that only the thickness of the gate oxide film of the P-channel transistor 83 is different from that of other transistors, the manufacturing process may be complicated. PA1 (b) During the reading operation, since a voltage of 5V is applied to the selected word line, 5V or more is required for the substrate potential of the P-channel transistor 83. In this state, for applying the ground potential to the unselected word line through the P-channel transistor, the P-channel transistor is operated under the condition such that the substrate bias voltage of 5V or more is applied thereto. Therefore, since the conductance gm of the P-channel transistor becomes low to reduce the operating speed of the word line driver, it is impossible to increase the operating speed of the row decoder circuit. As noted earlier, the P-channel transistor has a thick gate oxide film, which is disadvantageous for increasing the operating speed of the row decoder circuit. PA1 (c) There have been provided EEPROM applications operated by batteries such as portable computers. In the field, it is impossible to reduce stand-by current to zero.
For eliminating the problems (a) and (b), a technique of applying a negative voltage to the control gate 76 during erasing has been proposed by Sameer Haddad, et al., "An Investigation of Erase-Mode Dependent Hole Trapping in Flash EEPROM Memory cell," IEEE Electron Device Letters, Vol. 11, No. 11, November 1990, pp. 514-516, N. Ajika, et al., "A 5 VOLT ONLY 16M BIT FLASH EEPROM CELL WITH A SIMPLE STACKED GATE STRUCTURE," IEDM 90-115, and other related literature. In the technique, for example, -10V is applied to the control gate 76, and, for example, 5V is applied to the source region 72, thereby erasing the data by the tunnel current.
One advantage of the technique is that the junction breakdown voltage at the source side may be low because the voltage applied to the source region 72 during erasing is low. Therefore, it is not necessary that the depth of the source region is made deeper than that of the drain region, or that the impurity concentration of the source region is reduced. Accordingly, it is possible to reduce the gate length of the cell.
During erasing, band-to-band tunneling current (B--B current) flows from the source region 72, and the current value becomes several mA in the whole chip. Therefore, it is difficult to use a step-up circuit. Accordingly, a high voltage V.sub.pp for erase must be supplied from an external circuit in the prior art, thereby limiting the application range of EEPROMS. However, it is possible to supply the source voltage from the ordinary power supply V.sub.CC during erasure, which provides the advantage of using a 5V single power supply.
Because of its great advantages, the technique described above will be dominant in the future EEPROMs.
A circuit technique of applying a negative voltage to the gate has been proposed by S. D'Arrigo, et al., "A 5V-only 256K Bit CMOS Flash EEPROM (FIG. 5)," ISSCC 89, pp. 132-133. As disclosed here, a word line driver is electrically separated from a word line by a P-channel transistor whose gate is supplied with a negative voltage.
An example of such a circuit is shown in FIG. 8. In the circuit, an ordinary CMOS word line driver is provided by a P-channel transistor 81 and an N-channel-transistor 82, and a P-channel transistor 83 is inserted between the output node (the connection node with the word line WL) and the N-channel transistor 82. A negative voltage is applied to the gate of the P-channel transistor 83 during other modes except the erase mode, and the same electric potential as that of the well is applied to the gate thereof during the erase mode. The word line WL is connected to a negative charge pump circuit 85 via a P-channel transistor 84 whose source and gate are connected to each other.
This circuit acts normally as a word line driver. During the erasing operation, the P-channel transistor 81 is turned off to apply a negative voltage to the word line WL through the P-channel transistor 84 from the negative charge pump circuit 85, and the same electric potential as that of the well is applied to the gate of the P-channel transistor 83, thereby turning off the P-channel transistor 83. In this case, since only the P.sup.+ -type diffused regions of the P-channel transistors 81, 83, and 84 are connected to the word line WL, a forward-biased PN junction is not provided even if a negative voltage is applied to the word line WL.
However, the following problems occur in the circuit technique of separating the word line WL from the N-channel transistor 82 by using the P-channel transistor 83.
These problems (a), (b), and (c) will be explained in more detail.